-the PHY architecture development for USB/PCIe/Ethernet standards -integration of PHY with controlle -modeling of PHY with Verilog 1.Experience in high speed design building blocks for High Speed Interfaces, SERDES, PLL, CDR,
RTL logic design, Synthesis, Physical design, Power analysis and/or integration aspects for IO PHY in SoC 2.Over 3-year digital design experiences with PCIe/ USB/ DDR/ Ethernet 3. Can solve complex, novel and non-recurring problems. 待遇面議 員工20人 Job Summary: Designing analog and mixed-signal ICs for Power
Management Products utilizing leading edge sub-micron BiCMOS /DMOS technologies. Products to be designed may include, switching regulators, display drivers, audio amplifiers and power management ICs for fast-growing portable and non-portable markets such as broadband modems, PDAs, notebooks, cell phones, telecom, fiber optics, digital camera, network equipment, and automotive. Essential Functions: • Works on product definition, circuit synthesis from the transistor/resistor level up to the
system level, simulation, layout supervision • Participates in the entire product development cycle, from product definition through product release. Qualifications: • MSEE / PhD of electronic engineering, analog or digital IC design topics • For analog, familiar to power converter (buck/boost/buck-boost/LDO) analog design will be the plus • Self-motivated, could have strong team work/collaboration with overseas colleges. 待遇面議 外商公司 員工180人 設計MCU專用IO/ESD電路，包括競爭力分析、規格制定、電路設計、電路佈局指導、測試計畫等 --------------------------------------------------------------------------------------- 雅特力科技創立於2016年，為智原科技子公司。 【Artery雅特力】即將在台上市的IC設計公司，主要產品為32bit ARM core base MCU 公司網址：https://www.arterychip.com
關於雅特力：https://www.104.com.tw/company/1a2x6blojm 待遇面議 員工125人 -Responsible for entire analog design implementation that covers design specification,
design creation, integration and optimization to layout review, final post-layout simulation, silicon characterization and system test and debug. -Experience in analog IP development that include ADC, DAC, Audio Codec, PLL, IO, memory, analog blocks and high speed PHY for 130nm, 90nm and below technologies. -Knowledge in high speed PHY design (PCIE, USB, GbE, DDR) is an added advantage. -Preferably done some test characterization, measurement and compliance in previous employment 1.Must have
in-depth knowledge in circuit and logic IP design flow with hands-on experience in design and development, mixed signal design and simulation verification, IP test/characterization, low power high speed design methodology. Scripting in Perl, TCL, Unix, Linux 2.The ability to work with multiple team members 3.Working experience in EDA tools such as Synopsys Design Compiler, Physical Compiler, PrimeTime etc is a plus. 待遇面議 員工20人 11/03 電源管理IC設計工程師
【工作內容】 1. 負責和管控類比電源IC之設計/模擬/驗證/除錯等流程，追蹤相關流程進度 2. 撰寫各設計流程之設計/除錯分析報告 【必要條件】 1. 熟悉電子電路、電源類比IC和交換式電源IC設計 2. 熟悉Cadence IC6 或 HSPICE Simulation Design Flow 3. 對電源IC設計有熱忱、能獨立作業和具當責態度 待遇面議 員工90人 11/03 RF 量測工程師
1. IC 功能測試與實驗。 2. 架設實驗環境及備品管理。 3. 協助研發部門所有相關工作。 月薪32,000元以上 員工20人 11/03 RF IC設計工程師(竹北)
1. RF Integrated circuit design (IC設計) 2. Front end module(前端模組)設計 3. RF 測試應用與除錯 4. 熟RF PA, LNA與Switch設計者佳 5. 電子電機相關科系畢，具電磁波、半導體及微波工程等相關知識 6. 客戶技術支援 待遇面議 員工20人 11/03 IC營運生產工程師
1.產品電路設計、驗證、進出爐(HTOL/HAST/THB/BLT) 2.電路焊接 3.每月依績效表現額外發放點數獎金 4.表現優秀，培養二年後年薪可破百萬 月薪34,000~45,000元 上市上櫃 員工700人 11/03 【年薪不低於150萬】類比IC設計工程師 - 智原科技子公司
1. Main responsibility is to design analog IPs in MCU such as adc/dac, pll, osc, por, ldo 2. Responsible for analog IP design, verification plan, test plan, document 3. Communicate with system, layout and digital engineer to ensure high quality --------------------------------------------------------------------------------------- 雅特力科技創立於2016年，為智原科技子公司。 【Artery雅特力】即將在台上市的IC設計公司，主要產品為32bit ARM core base MCU 公司網址：https://www.arterychip.com 關於雅特力：https://www.104.com.tw/company/1a2x6blojm 待遇面議 員工125人 11/03 [板橋]AC/DC類比IC設計工程師
通嘉致力打造工作/生活/健康兼具的職場環境，歡迎你加入展開「通嘉就是你家」旅程! 本職務負責工作如下： 1. 負責類比電源IC之設計/模擬/驗證/除錯 2. 管控類比電源IC之設計/模擬/驗證/除錯..等流程，追蹤相關流程進度 3. 撰寫各設計流程之設計/除錯分析報告 【必要條件】 1. 熟悉電源類比IC設計or Switching power converter 2. 熟悉電子電路 3. 熟悉HSPICE Simulation and Design Flow 4. 對電源IC設計有熱忱者，能團隊作業，具當責態度 待遇面議 員工200人 距捷運板橋站380公尺 11/03 資深類比IC設計工程師(audio codec design)(台北)
1. Sigma delta ADC/ DAC design for Audio application 2. Deliver document for SOC integration 3. Provide Analog IP MP solution in CP/FT. 4. Analog IP ES validation 待遇面議 上市上櫃 員工500人 距捷運西湖站110公尺 11/03 研發類--Flash memory/Analog Design Engineer(竹北)
【邀請您將104履歷同步上傳至華邦官方網站，將使您的履歷優先被主管看見】 此職缺履歷登錄網址：https://bit.ly/3x5Attf 1. Analog Circuit Design & Simulation 2. NOR Flash Circuit Verification & Debug 3. NOR Flash silicon verification & quality improvement 待遇面議 上市上櫃 員工2800人 11/03 產品工程師
1.產品Datasheet了解及製作、驗證。 2.打線圖驗證(Bonding Diagram) 3.新產品驗證/測試以及撰寫應用技術文件。 4.對封裝廠文件溝通介面 5.對產品規格的驗證及確認。 6.產品良率分析、提升、製程及成本改善分析。 7.產品可靠性分析與改善。 8.產品失效分析及客訴問題協調解決。 9.外包商工程管理與問題解決，生產流程異常處理及資料分析。 月薪32,000~42,000元 員工25人 11/03 RF IC TX designer
1. Take care of CMOS RF IC design. 2. Familiar with TX front-end. 3. Familiar with bluetooth or WiFi system or mmW design will be better. 待遇面議 11/03 Analog IC designer
具備1~4之中1種以上的設計經驗。 1. 放大器應用電路; band-gap, op-amp, filter, etc. 2. 電源類比電路: DCDC, LDO, charge-pump, etc. 3. 信號處理電路: SAR ADC, sigma-delta ADC, DAC, etc. 4. 時脈產生電路: PLL, DLL, frequency synthesizer, etc. 待遇面議 11/03 RD Team_Analog Layout Engineer_類比IC佈局工程師
Job Summary: Layout Engineer will work directly and indirectly with Design / CAD / Layout Manager in development of Mixed-Signal and Analog Integrated Circuits. Individual perform job professionally and independently. The following are the requirements for this job function. Essential Functions: • Chip Planning • Project Schedule / Layout Schedule Estimation • Device Placement on block level according to matching requirements • Block implementations on Top Level • Top Level connections • Signal matching / sensitive nets shielding technique • Chip power / ground planning • Integration of Analog top with Auto-Placement-Routing • Pad / ESD rule and routing / connection • Database DRC & LVS verifications on either DIVA or Dracula basis • Chip Tape-out in accordance with company’s Tape-out Procedure • Positive Attitude Qualifications: • 2+ years Layout experience in Analog and/or Mixed-Signal Circuit Design • Ability to do chip plan, estimate die size and project schedule • Ability to resolve DRC & LVS data verification and tape out chip independently • Familiarity with fundamentals of analog processes • Experience with Cadence and/or VIRTUOSO tools preferable 待遇面議 外商公司 員工180人 11/03 Analog IC Design Engineer
【工作內容】 1. 負責Serdes PHY Ex. DP/HDMI PHY的開發與維護工作。 2. 高速 PLL 與 RX Front End 的類比電路開發工作 3. Type-C / PD Controller的類比電路開發工作 【需求條件】 1. 碩士以上，電子電機、電機與控制、電信相關科系畢業。 2. 具三年以上USB、SATA、PCIE、HDMI、DisplayPort等PHY相關技術領域設計開發經驗者佳。 3. 碩士研究題目為PLL或 Serdes相關領域之應屆者可。 待遇面議 |
類比IC 工程師
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